1. Field of the Invention
Embodiments of the invention relate to a semiconductor device. More particularly, embodiments of the invention relate to a method and apparatus for controlling two or more non-volatile memory devices.
2. Discussion of Related Art
Read and write speeds associated with semiconductor memory devices influence overall system speeds. Non-volatile memory devices include read-only memories (ROM), electrically erasable and programmable ROM (EEPROM), and erasable and programmable ROM (EPROM) devices. Because EEPROMs can electrically erase and program data, they have been used for system programming applications requiring continuous updates or auxiliary memory devices. In particular, flash EEPROM devices (hereinafter, referred to as flash memory devices) have a higher degree of integration than existing EEPROM devices and may be used for large-capacity auxiliary memory devices.
FIG. 1 is a block diagram of a memory system 10 including a plurality of conventional semiconductor memory devices 11, 12, 13, and 14. Each of the semiconductor memory devices 11-14 is a NAND flash memory device which includes an input/output (I/O) pin for inputting/outputting 8-bit I/O data I/O[7:0], a plurality of pins (i.e., nCEi pins, nRE pins, and nWE pins) for receiving a plurality of control signals nCEi (where i=1, 2, 3, or 4), nRE, and nWE, and a ready/busy (R/B) pin. A chip enable signal nCEi selects one of the semiconductor memory devices 11-14. Different chip enable signals nCEi are used to select different semiconductor memory devices 11-14, respectively. When the chip enable signal nCEi is at a high logic level, the semiconductor memory device receiving the chip enable signal nCEi is in standby mode. When the chip enable signal nCEi is at a low logic level, the selected semiconductor memory device is in an active mode. Read enable signal nRE controls data output. After a predetermined period of time after the falling edge of read enable signal nRE, data I/O[7:0] is sequentially output. Write enable signal nWE controls the input of an address, command or data signal. The command, address or data signal is latched in response to a rising edge of write enable signal nWE. The I/O pin is also used to input the address and command signals.
NAND flash memory devices can use input pins in common for an address, command and data signals because a data I/O period and an address/command input period are separated in the time domain. When a chip (or a memory device) is not selected or when outputting is impossible, the I/O pin is floated with high impedance. The R/B pin is an output pin for reporting the operating state of a memory device to a controller. The R/B pin is at a low level while the memory device is performing a program, erase or read operation and returns to the high level when the operation is completed.
FIG. 2 is a timing diagram of signals when data is output from the memory system 10 illustrated in FIG. 1. Generally, data read and program operations are performed in units of pages in NAND flash memory devices. Accordingly, when one-data page is read from each of the NAND flash memory devices 11-14, first memory device 11 is selected and one-page of data is read from the first memory device 11 and then the second memory device 12 is selected and one-page of data is read from the second memory device 12. In a state where first memory device 11 is selected by activating the first chip enable signal nCE1 for a predetermined period of time (e.g., time needed to read one-page data), the read enable signal nRE is toggled so that the one-page of data is read from first memory device 11. In a state where second memory device 12 is selected by activating the second chip enable signal nCE2 for the predetermined period of time, read enable signal nRE is toggled so that the one-page of data is read from second memory device 12. The same procedure is performed with respect to the third and fourth memory devices 13 and 14.
As described above, in conventional memory systems a read enable signal is toggled repeatedly while a chip enable signal is activated so that the read or write operation is performed in units of pages. Data I/Ox is output after an access time determined based on a falling edge of the read enable signal nRE. A cycle of the read enable signal nRE may be determined by a minimum cycle of a controller (not shown) for controlling memory devices 11-14 or test equipment (not shown). When the minimum cycle of the controller or the test equipment is 80 ns, the cycle of the read enable signal nRE cannot be shorter than 80 ns as illustrated in FIG. 2. Thus, the read cycle is also 80 ns. Accordingly, it takes 655,360 ns (=80 ns×2048×4 (the number of chips)) to read one-page of data from all of the memory devices 11-14.
FIG. 3 is a timing diagram of signals when data is written (or input) to the memory system 10 illustrated in FIG. 1. This timing diagram is similar to that illustrated in FIG. 2, with the exception that the write enable signal nWE is toggled instead of the read enable signal nRE. Input data I/Ox is latched in response to a rising edge of the write enable signal nWE. A write cycle is determined based on the operating cycle of a controller or test equipment. When the write cycle is 80 ns, it takes 655,360 ns (=80 ns×2048×4 (the number of chips)) to write one-page of data to all of the memory devices 11 through 14. According to the above-described conventional memory devices, even when the operating cycle of a memory device is shorter than that of a controller or test equipment, the read/write speed is determined by the operating cycle of the controller or the test equipment. As a result, read/write performance may be degraded.